In recent years, with a view to producing large-sized and high-resolution liquid crystal display devices, fast and high-resolution image sensors of a close-contact type, three-dimensional ICs and the like, attempts have been made at forming a high-performance semiconductor element on an insulative substrate such as glass.
In order to form such a semiconductor element, it is necessary to form a thin-film layer of semiconductor. It has been known to form a semiconductor element on an insulative substrate by using a semiconductor thin film composed of an amorphous silicon semiconductor (a-Si) or using a semiconductor thin film composed of a crystalline silicon semiconductor such as polycrystalline silicon or microcrystalline silicon.
Among others, amorphous silicon semiconductor thin films are most commonly used because they can be formed at a relatively low temperature by using a vapor deposition technique and they provide good mass producibility. However, amorphous silicon semiconductor thin films are inferior in physical characteristics such as electrical conductivity. Therefore, amorphous silicon semiconductor thin films are not suitable for, for example, the aforementioned devices whose semiconductor elements are required to show excellent performance.
On the other hand, crystalline silicon semiconductor thin films have excellent electrical conductivity. Therefore, various research and development efforts have been made to seek applications for the aforementioned devices, among others. The following methods are known techniques for obtaining a thin film of crystalline silicon semiconductor:
(1) Directly form a crystalline silicon semiconductor film at the time of film formation.
(2) Form an amorphous silicon semiconductor film, and then irradiate the film with intense light to crystallize the amorphous silicon by virtue of this energy.
(3) Form an amorphous silicon semiconductor film, and then crystallize the amorphous silicon by applying thermal energy thereto.
In method (1), silicon crystallization progresses concurrently with the film formation process; therefore, the thickness of the film to be formed must be sufficiently large to be able to obtain a crystalline silicon having a large crystal grain size. Therefore, this method presents a technical difficulty when forming a crystalline silicon semiconductor thin film having good semiconductor characteristics over the entire surface of a substrate which has a large area. Moreover, since it is necessary to perform the film formation at a temperature of 600° C. or above, it is impossible to use a glass substrate, which is inexpensive and has a low softening point, as an insulative substrate. This presents a problem in terms of production cost.
Method (2) utilizes the crystallization phenomenon during the melting/solidification process. Therefore, while the resultant crystal grain size may be small, grain boundaries are well taken care of, so that a high-quality crystalline silicon semiconductor can be obtained. However, it may be difficult to provide a practical means for irradiating intense light over a large area. For example, in the case of employing an excimer laser (which is a most common choice at present), the stability of laser light is insufficient. Therefore, it is difficult to obtain a crystalline silicon film by applying a uniform process over the entire face of a substrate which has a large area. This makes it difficult to form a plurality of semiconductor elements having uniform characteristics on the same substrate. Moreover, the irradiation area of laser light is small, thus leading to poor production efficiency.
Method (3) has an advantage in that a crystalline silicon semiconductor film having a large area can be obtained more easily than in the case of employing method (1) or (2). However, crystallization requires a heat treatment at a temperature as high as 600° C. or more to be performed for several tens of hours. Therefore, if the heat treatment were to be conducted at a lower temperature in order to employ an inexpensive glass substrate, the heating time would have to be increased, which would result in a lower throughput. On the other hand, this method utilizes a solid phase crystallization phenomenon, so that the crystal grains spread in a direction parallel to the substrate plane, thus attaining a crystal grain size as large as several micrometers. However, since grain boundaries are formed through collision of the crystal grains that have grown, the grain boundaries may serve as trap levels for carriers, thus reducing electron mobility.
Among the above three methods, method (3) is drawing particular attention as a promising technique. As applications of method (3), methods for forming a highly uniform and high quality crystalline silicon film through a heat treatment which is performed at a lower temperature and for a shorter amount of time are disclosed in, for example, Japanese Laid-Open Patent Publication No. 6-333824, Japanese Laid-Open Patent Publication No. 6-333825, and Japanese Laid-Open Patent Publication No. 8-330602.
According to the methods disclosed in the aforementioned laid-open patent publications, a minute amount of metallic elements such as nickel is introduced at the surface of an amorphous silicon film and a heat treatment is performed. Thus, these methods enable crystallization at a low temperature of 600° C. or less, with only a short processing time on the order of several hours.
According to the above methods, presumably, crystal nuclei based on the introduced metallic elements are generated at an early stage of the heat treatment, and thereafter the crystal growth of silicon is prompted by the metallic elements serving as a catalyst, whereby crystallization progresses rapidly. In this meaning, the introduced metallic elements are referred to as “catalytic metals”. A silicon film which has been crystallized by using a usual solid phase growth technique has a twin crystal structure. In contrast, a crystalline silicon film obtained by the above methods is composed of a number of columnar crystals, such that the interior of each columnar crystal takes a near monocrystalline state.
According to the above methods, normal semiconductor element characteristics cannot be obtained if any catalytic metals are left in the silicon film. Therefore, as disclosed in Japanese Laid-Open Patent Publication No. 6-333824 and Japanese Laid-Open Patent Publication No. 8-236471, the catalytic metals are typically captured (“gettered”) by using phosphorus ions or the like. Specifically, catalytic metals are introduced, and after patterning of a crystalline silicon film which has been obtained through a heat treatment, a gate insulating film is provided on the surface thereof and a gate electrode is further provided. Then, the crystalline silicon film is further patterned by using the gate electrode as a mask, and thereafter the crystalline silicon film is doped with phosphorus ions. Thus, any regions (i.e., source and drain regions) other than the region immediately underlying the gate electrode is doped with phosphorus. By activating the phosphorus by means of thermal energy or laser light, the catalytic metals which are present in the region immediately underlying the gate electrode are gettered at the source and drain regions, whereby a thin film transistor is formed whose channel region is the region immediately underlying the gate.
The above-described phosphorus ion doping must be performed for a crystalline silicon film having a large area. Therefore, an ion doping apparatus which is capable of irradiating an ion beam occupying a large area is employed. In such an ion doping apparatus, in order to generate a large amount of ions and generate an ion beam with a large area, an ion beam which is generated by decomposing a material such as diborane or phosphine at an ion source is irradiated onto a crystalline silicon film, without employing a mass separator. Such an ion doping apparatus is also employed when implanting a minute amount of boron ions into the channel region in order to control the threshold voltage of the thin film transistor. In the case where ion doping is to be performed over an area which is broader than the ion beam, an ion beam is scanned relative to the substrate by allowing either the ion beam or the substrate to move.
When fabricating a thin film transistor by using this conventional type of ion doping apparatus, precision of the phosphorus or boron ion implantation greatly affects factors such as resistance of the source and drain regions, gettering ability of the catalytic metals, threshold voltage, reliability characteristics, uniformity (uniformity of characteristics), and/or yield. In particular, in order to control the threshold voltage and reliability characteristics, it is necessary to control the ion implantation with an enhanced precision.
Conventional ion doping apparatuses control ion implantation by adjusting the acceleration voltage and dose (implanted amount). However, merely adjusting these factors would not realize adequate control of the ion species ratio and implanted amount of the generated ion species, so that it would be difficult to fabricate transistors whose threshold voltage and reliability satisfy required specifications while preventing fluctuations and maintaining a high yield.
In particular, in conventional ion doping apparatuses, the substrate scanning speed is determined and ion implantation is begun while the ion beam that has been taken out from the generated plasma still has an unstable beam current density. Therefore, the ion beam current density may vary during the scanning. As a result, there is a problem in that the implanted amount may shift substantially, thus causing the TFT characteristics to fluctuate.
Moreover, if the ion beam current density happens to be on a temporary increase at the moment of determining the scanning speed, the scanning speed which is determined from the ion beam current density may be so fast that it cannot be controlled by the apparatus. In such cases, the ion doping apparatus will detect abnormality and stop operating, thus resulting in a reduced availability.
On the other hand, in a case where the ion implantation is controlled so as to begin once the ion beam current density becomes stable (i.e., without necessarily reaching a predetermined value), the ion species ratio may fluctuate even while the ion doping apparatus is being operated under the same conditions. In this case, the controllability of low-concentration doping of boron ions for the channel portion (which requires especially precise implantation control) and low-concentration doping of phosphorus ions for an LDD region is deteriorated, thus making it difficult to control the threshold voltage and the reliability characteristics to desired values. This also results in a decrease in the production yield of the thin film transistor.